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| CCD Delay Line Series MN3880S NTSC CCD Video Signal Delay Element Overview The MN3880S is a CCD signal delay element for video signal processing applications. It contains such components as a shift register clock driver, charge I/O blocks, two CCD delay elements, a clamp bias circuit, resampling output amplifiers, and booster circuits. The MN3880S samples the input using the supplied clock signal with a frequency of 7.15909 MHz, twice the NTSC color signal subcarrier frequency, and after adding in the attached filter delay, produces independent delays of 1 H (the horizontal scan period) each for the two lines. Pin Assignment VBIASC VOC N.C. VDD -VBB N.C. 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 VINC N.C. N.C. X1 VSS N.C. N.C. VINY Features Single 4.9 V power supply Single chip combining luminance signal delay element and delay element for chrominance signal after passing through a low pass filter VOY VBIASY (TOP VIEW) SOP016-P-0225 Applications VCRs 1 MN3880S Block Diagram CCD Delay Line Series 12 4 Bias circuit VINC 16 Charge input block Charge detection block Resampling output amplifier 2 CCD 454 stages 1 VBIASC VDD VSS VOC oS driver o1 driver o2 driver oR driver oSH driver oSH driver Timing adjustment XI 13 Waveform amplitude adjustment block Timing adjustment oS driver o1 driver o2 driver oR driver oSH driver oSH driver Clamp circuit VINY 9 Charge input block 5 Charge detection block Resampling output amplifier 8 7 VOY CCD 454 stages -VBB 2 VBIASY CCD Delay Line Series Pin Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Symbol VBIASC VOC N.C. VDD -VBB N.C. VOY VBIASY VINY N.C. N.C. VSS XI N.C. N.C. VINC Pin Name Output gate connection (C) Signal output (C) No connection Power supply Substrate connection No connection Signal output (Y) Output gate connection (Y) Signal output (Y) No connection No connection GND Clock input No connection No connection Signal output (C) MN3880S Remarks Negative voltage pin 3 MN3880S Application Circuit Example 10F - + CCD Delay Line Series VBIASC (0.01F) 12 VSS 0.1F 4 VDD Bias circuit VINC 16 (0.01F) Charge input block CCD 454 stages Charge detection block Resampling output amplifier 2 VOC oS driver o1 driver o2 driver oR driver oSH driver oSH driver Timing adjustment XI 13 1000pF Waveform amplitude adjustment block Timing adjustment oS driver o1 driver o2 driver oR driver oSH driver oSH driver Clamp circuit VINY 9 -+ 0.47F Charge input block -VBB 5 1 CCD 454 stages Charge detection block Resampling output amplifier 8 7 VOY (0.01F) VBIASY (0.01F) Note: If the external capacitor attached to pin 5 is an electrolytic capacitor, attach the negative pole to pin 5. 4 CCD Delay Line Series Package Dimensions (Unit:mm) SOP016-P-0225 MN3880S 10.100.20 16 9 1.100.20 4.300.20 6.500.20 1 8 1.500.20 1.60 -0.20 +0.50 0.15 -0.05 +0.10 0 to 10 0.40min. (0.6) 1.27 0.400.10 SEATING PLANE 0.100.10 5 |
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